This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to a one-transistor dynamic read/write memory of the N-channel silicon gate type.
Dynamic read/write memory cells made by the double-level polysilicon N-channel self-aligned process commonly used in the industry are shown in pending U.S. Pat. applications Ser. No. 648,594, filed Jan. 12, 1976 and now abandoned, and Ser. No. 722,841, filed Sept. 13, 1976 and now U.S. Pat. No. 4,240,092, by C-K Kuo, both assigned to Texas Instruments, as well as in Electronics, Feb. 19, 1976, pp. 116-121, May 13, 1976, pp. 81-86, and Sept. 28, 1978, pp. 109-116.
One of the continuing problems with the standard dynamic RAM cell is that of thin oxide failures. Both the transistor and the capacitor in each cell are polysilicon layers separated from the silicon by thin silicon dioxide. As the bit density increases the cell geometries are scaled down, thus requiring thinner oxides and causing an increase in thin oxide failure problems. One transistor dynamic cells using PN junction capacitors instead of MOS capacitors eliminate a large part of the thin oxide, but processes previously used for this purpose resulted in cell sizes which were too large for present density requirements.
The double-level polysilicon process which is widely used for semiconductor memory manufacture produces access transistors for one-transistor cells wherein the channel length is dependent upon mask alignment. This fact causes variations in the characteristics of access transistors, and again this problem increases as the transistor size is scaled down.
Another problem in prior dynamic memory cells is errors induced by ambient alpha particles. Storage capacitors can be discharged by this radiation, causing "soft" errors.
It is the principal object of this invention to provide an improved method of making dynamic read/write memory devices. Another object is to provide an improved manufacturing method for semiconductor devices of reduced cell size. An additional object is to provide a dense array of memory cells, made by a more reliable method, particularly with reduced thin oxide failures. A further object is to provide an improved way of making capacitors in memory cells. Another object is to provide alpha particle protection in memory cells.